The present invention relates generally to the fabrication of integrated circuits (IC""s), and more particularly to the fabrication of memory IC""s.
Semiconductor devices are used in a variety of electronic applications, such as personal computers and cellular phones, for example. One such semiconductor product widely used in electronic systems for storing data is a semiconductor memory, and one common type of semiconductor is a dynamic random access memory (DRAM).
A DRAM typically includes millions or billions of individual DRAM cells, with each cell storing one bit of data. A DRAM memory cell typically includes an access field effect transistor (FET) and a storage capacitor. The access FET allows the transfer of data charges to and from the storage capacitor during reading and writing operations. In addition, the data charges on the storage capacitor are periodically refreshed during a refresh operation.
Another memory semiconductor device is called a ferroelectric random access memory (FRAM). An FRAM typically has a similar structure to a DRAM but is comprised of materials such that the storage capacitor does not need to be refreshed continuously as in a DRAM. Common applications for FRAM""s include cellular phones and digital cameras, for example.
The semiconductor industry in general is being driven to decrease the size of semiconductor devices located on integrated circuits. Miniaturization is generally needed to accommodate the increasing density of circuits necessary for today""s semiconductor products. As memory devices such as DRAMs are scaled down in size, various aspects of manufacturing DRAM IC""s are becoming more challenging. For example, extreme aspect ratios (the ratio of the vertical depth of a trench to the horizontal width) in small-scale devices present etch and deposition process challenges.
Insulating materials, for example, SiO2, are used to isolate conductors and other active regions in semiconductor devices. In the prior art, in back-end-of-line (BEOL) applications, e.g. for insulation for metal lines, a plasma enhanced chemical vapor deposition (PECVD) process based on a tetraethoxysilane (TEOS) source precursor was typically used for the deposition of insulating material, which resulted in an isotropic or conformal deposition profile. An anisotropic etch was used, such as a physical sputter etch, to remove the insulating material overhangs that covered areas that needed to be filled, and another insulating layer was deposited, e.g., by PECVD.
A technique used to deposit insulators that is being used more frequently in densely-packed semiconductor devices having small feature sizes is high density plasma (HDP) chemical vapor deposition CVD. HDP-CVD has been used in the BEOL in the past, and is also being used in the front-end-of-line (FEOL) for shallow trench isolation (STI). However, HDP-CVD is proving a challenge with today""s rapidly increasing high aspect ratio features, which are approaching 4:1 and higher.
FIG. 1 illustrates a prior art semiconductor device 10 having isolation trenches 11 formed in a substrate 12, the isolation trenches 11 having a relatively high aspect ratio. The aspect ratio refers to the ratio of the height (h) compared to the width (w) between the isolation trenches 11, and is expressed as a ratio of h:w, e.g., 3:1 or 4:1.
The semiconductor device 10 in this example comprises a DRAM device, where the trenches 11 comprise isolation trenches (IT""s) that are adapted to electrically isolate element regions of a DRAM chip, for example. The element regions may comprise active areas, storage capacitors, transistors, and other electronic elements, as examples. The process of forming IT""s is often also referred to in the art as shallow trench isolation (STI), for example.
Prior to formation of the isolation trenches 11 within the substrate 12, a pad nitride 14 may be deposited over the substrate 12. An insulating layer 16 is deposited over the semiconductor wafer 10 using HPD-CVD to fill the trenches between the active areas, as shown. Because of the high aspect ratio h:w which may be 2:1 or greater, the HDP-CVD process may result in voids 20 that form within the trenches 11, as shown. This occurs because an insulator 16 deposited by HDP-CVD has a tendency to form cusps or huts 18 at the vicinity of the top portion of the trenches 11. This results in a greater thickness of the insulating layer 16 on the sidewall at the top of the trenches 11 compared to the sidewall deposition in the lower portion of the trenches 11. As a result, the top of the insulating layer 16 nearer the huts 18 closes, preventing the void regions 20 from being filled. The insulating layer 16 peaks xe2x80x98pinchxe2x80x99 the flow of insulating material 16 reactants into the trenches 11.
A problem in prior art isolation techniques is the formation of these voids 20 in high-aspect ratio trenches. Aggressive aspect ratios in DRAM devices are approaching 4:1 and greater. The gap fill requirement is a function of ground rule layout and critical dimension (CD) tolerances, for example.
As the minimum feature size is made smaller, the oxide gap fill of isolation trenches 11 becomes more challenging, especially in devices such as vertical DRAMs. Leaving voids 20 in a finished semiconductor device may result in device 10 failures. Voids 20 may inadvertently be filled with conductive material in subsequent processing steps such as gate conductor deposition, for example, which may short elements in the substrate.
What is needed in the art is a method of providing isolation and depositing insulating material between high aspect ratio trenches in today""s densely-packed semiconductor devices.
The present invention achieves technical advantages as a method of filling high aspect ratio gaps in semiconductor devices. A first anisotropic insulating layer is deposited and etched with an isotropic etch to remove the first insulating from the sides of the trenches. Additional anisotropic insulating layers are deposited as required for the particular aspect ratio of the trench in order to fill the trench completely without leaving voids within the trench insulating material.
Disclosed is a method of filling gaps between features of a semiconductor wafer, the gaps having sidewalls, the method comprising depositing a first anisotropic insulating material over the wafer to partially fill the gaps, removing the first anisotropic insulating material from at least the gap sidewalls, and depositing a second anisotropic insulating material over the wafer to at least partially fill the gaps.
Also disclosed is a method of isolating element regions of a semiconductor memory device, the memory device including a plurality of isolation trenches separating a plurality of element regions, and the isolation trenches including sidewalls. The method comprises depositing a first insulating material over the isolation trenches, removing a portion of the first insulating material from at least over the isolation trench sidewalls, and depositing a second insulating material over the trenches.
Advantages of embodiments of the present invention include providing a method of filling high aspect ratio gaps in semiconductors such as vertical FETs. A silicon nitride liner may be deposited over the trenches prior to the first insulating layer deposition so that an etch selective to nitride may be used to remove the first insulating layer from the side of trenches in an isotropic etch. The top portion of the silicon nitride liner may be removed prior to the deposition of the top insulating layer, which prevents divot formation on the top surface that may occur during the pad nitride removal. Because only one type of insulating deposition tool is required, the invention does not add an inordinate amount of complexity to the manufacturing process. An inexpensive process such as a wet etch process may be used to remove the insulating layers from the isolation trench sidewalls. The active areas of semiconductor devices are scalable in accordance with the present invention; that is, the number of insulating layers may be varied or increased in accordance with the trench aspect ratio required.